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SiFive Unveils 64-Bit RISC-V Server Core

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文章创建人 Iczoom

Original Title:SiFive Unveils 64-Bit RISC-V Server Core


  The chipmaker's latest processor core is its biggest to date. Can it succeed where Arm cores have so far failed?

  SiFive’s just announced Performance P650 RISC-V processor core is aimed at high-end servers and other applications requiring large arrays of multiple processor cores.

  The P650 processor core is a 64-bit implementation of the RISC-V architecture with an out-of-order pipeline and advanced branch prediction. The new RISC-V core arrives months after SiFive introduced its Performance P550 processor core.

  The P650 brings a pair of attributes placing it within the realm of high-end server processors. First, SiFive has made specific performance enhancements to the processor architecture, including a 4-wide instruction dispatch (increased from the P550 core’s 3-wide dispatch) to three execution units. The Performance P650 core has a 13-stage load/store pipeline and a separate, 10-stage integer execution pipeline.


  (Click on image to enlarge.)

  SiFive was mum about floating-point capabilities for the core in its public statement, although the block diagram above shows a floating-point unit (FPU). During a presentation describing the Performance P550 core at the Linley Processor Forum in October, SiFive showed two slides that previewed a follow-on, next-generation processor core. One slide disclosed that the next-generation processor core would include a 64-bit, double-precision FPU and bit-manipulation extensions.

  To buttress its intended use as a server processor, the P650 core supports virtual software environments by implementing RISC-V “H” hypervisor instruction extensions. In addition, the new core is designed to be implemented in a more advanced process technology than the P550 core. SiFive claims that the targeted process node combined with the architectural and other design improvements give the P650 core a 50 percent performance boost over the P550 core.

  More than a processor core

  Among the second set of attributes required by high-performance servers, features that SiFive incorporated into its P650 processor core, is the capability to implement scalable, coherent, multicore processor clusters with four to 16 processor cores per cluster. Each P650 processor core has separate L1 instruction and data caches as large as 128 Kbytes, and some amount of L2 cache, split into two banks.

  SiFive did not disclose the maximum size of the L2 cache for the Performance P 650 core, but L2 cache on the earlier P550 core can be as large as 256Kbytes. That’s not much larger than the P650 core’s L1 caches, making it reasonable to expect the L2 cache maximum size to be somewhat larger for the new core.

  In fact, SiFive’s next-generation core preview slide revealed that the L2 cache could be as large as 2 Mbytes. Clusters of P650 processor cores also can share an L3 cache as large as 1 Mbyte per core. Presumably, that means a shared L3 cache as large as 16 Mbytes, given 16 processor cores.

  The earlier P550 core design creates multicore clusters through shared, multiport access to the L3 cache. Four Performance P550 cores share one L3 cache. The Performance P650 core will use an as yet undisclosed coherent interconnect to implement clustering, although details in SiFive’s announcement do mention “clean, coherent NoC interfaces.”

  SiFive’s preview showed a similar multiport cache configuration for a cluster of four P650 cores, and a second, next-generation preview shows four, 4-core clusters connected by a network-on-chip.

  In addition to the mechanics of coherent clustering, SiFive has engineered additional system hardware features for multicore P650 processor clusters such as platform-level memory management and interrupt control units, required to implement fully featured server processor clusters. Details released by SiFive also mention “advanced security and cryptographic features,” without elaborating.

  SiFive said it would offer select customers a P650 architecture preview in early 2022, with general availability by mid-year. Although SiFive mentioned none of these lead customers by name, Intel announced in June it would implement SiFive’s Performance P550 core for its Horse Creek platform. The Horse Creek platform would be implemented on Intel’s 7-nm process technology, rebranded as “Intel 4.”


  Still unanswered is the ecosystem question: Hardware alone does not win server processor sockets. That’s been a hard lesson for many companies aspiring to place Arm processor cores into servers. There’s already a growing list of failed projects that attempted to break into servers with Arm cores.

  Chip vendors that have tried and failed include AMD, Broadcom, Calxeda, Cavium, Huawei, Nvidia, Qualcomm, Samsung and Tianjin Phytium.

  Although Arm cores are making inroads into servers – the AWS Graviton, Fujitsu A64FX, and Marvell ThunderX and ThunderX2 processors among them – it’s been a slow process. Server processors based on the RISC-V architecture, including the SiFive P650 core, will meet similar, ecosystem-related resistance from server vendors and data center architects as SiFive and others attempt to displace the x86 processor architecture from its throne.

  SiFive zealots are nonetheless convinced that their favored architecture will eventually succeed.

  SiFive will provide more details about its Performance P650 processor core and future RISC-V-based cores during a presentation at next week’s RISC-V Summit 2021 in San Francisco.


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