# Circuit lets you test sample-and-hold amplifiers

Original Title：Circuit lets you test sample-and-hold amplifiers

Sample-and-hold amplifiers sample an analog voltage and hold it until an ADC can digitize it. A perfect sampling circuit holds a voltage until digitizing is complete. Thus, the amplifier’s output is identical to its input. Real sample-and-hold amplifiers, however, can gain or lose voltage, producing an error. Offset voltages in amplifiers cause a static additive error. Further, there occurs a specific additive error, the so-called voltage pedestal, which originates within the transition from the sample state to the hold state because of a parasitic charge transfer to the hold capacitor.

A sample-and-hold amplifier uses an analog switch to connect a signal to a holding capacitor. When the switch closes, thus having low resistance, the capacitor charges to the sampled input voltage. During the hold time, when the switch has high resistance, the sampling capacitor holds the voltage until the ADC digitizes it. During the transition from low to high switch resistance, a parasitic charge injection, mainly from the gate of the switch to the hold capacitor, continues to charge the capacitor until the switch’s control voltage reaches a steady logic level. The injected charge produces an error voltage at the capacitor. Additional errors may occur during the hold time. Leakage and bias currents in the amplifier combine with tens of picoamps of leakage current in the switch and capacitor to cause the capacitor to charge or discharge during hold time.

By applying a logic-control signal with a duty cycle of D and 1–D, you can measure a mean output voltage difference, [ΔVOUT ]=[VOUT –VIN ], which the following equations show. [ΔVOUT ]=VSTAT + (1–D)VINJ +½(1–D)²VDROPPEAK , and [Δ

]=VSTAT +DVINJ +½D²VDROPPEAK , where ΔVOUT and

Δ

are the output-voltage differences for D and 1–D, respectively; VSTAT is the steady output-voltage difference for a selected value of the reference input voltage, D is the duty cycle, VINJ is the voltage pedestal, and VDROPPEAK is the peak voltage drop. Figure 1 shows how the voltages in the equations change over time. If you apply a complementary control waveform with a duty cycle of 25%, you can measure another dc component of the sample-and-hold amplifier’s output voltage. Finally, when the sampling switch is continuously on, you can measure the VSTAT voltage, which is a real dc voltage. VOUT and

contain a waveform superimposed onto a selected value of the reference voltage. Thus, you should measure the mean values of these voltages using a series resistor with a value of, say, 10 k(Ω).

Multiplying the voltage pedestal, a simple rectangular waveform, by the duty cycle yields the average value. In contrast, the voltage-drop waveform appears as a sawtooth. Its mean rises as one-half of the duty cycle squared. The peak-voltage-drop value denotes a hypothetical voltage drop at the end of a whole period, T, of the SAMPLE/

logic-control waveform.

You can use the previous equations to find the values of the voltage pedestal and the peak voltage drop. A 75% duty cycle is a convenient value. The following equations are valid for this duty cycle: VINJ =6[ΔVOUT ]–2/3[Δ

]–16/3VSTAT , and VDROPPEAK =16[–[ΔVOUT ]+1/3[Δ

]+2/3VSTAT ]. You must find the optimal repetition rate, fREP , of the logic-control signal. As the optimal repetition rate increases, the difference in output voltage from the input is almost purely due to dc voltage offset plus the voltage pedestal: (

–VSTAT )/(VOUT –VSTAT )≈3. The following equation finds the maximum value for the optimal repetition rate: fREP ≤(0.01/4)×1/(tON –tOFF ), where tON and tOFF are the on and off times, respectively. This equation ensures that the difference in values between the turn-on and turn-off times of the sample-and-hold amplifier’s internal analog switch won’t affect the accuracy of the precision 25 and 75% duty cycles by more than 1%.

If you evaluate the equation for a high-performance analog switch, such as the Analog Devices ADG1213, you get a repetition rate of 33 kHz or less. The difference due to voltage drop prevails at low-value repetition rates. In this case, the repetition rate can be the value of the frequency at which

–VSTAT ≤1/10×VINMAX , where VINMAX is the maximum input-voltage range. The best way to determine the lower limit of the repetition rate is through experimentation.

A tested sample-and-hold amplifier using the circuit in Figure 2 uses a supply voltage of –1V, a drain-to-drain voltage of 5V, and a supply voltage of 3.3V for logic circuits in the pulse generator. Two sets of measurements at 25, 75, and 100% duty-cycle values for the AGD1213’s internal switch control used input voltages of 0 and 2.5V. You will measure the output-voltage difference, approximately –0.0366 mV, and the pedestal voltage, approximately –0.0333 mV, at a repetition rate of 1.762 kHz. The value of the residual effective charge injection, QINJ , into the hold capacitor, CH =2 nF, is QINJ =CH ×VINJ . The value is negative and doesn’t exceed –75 fC. The following equation defines the difference of charge injection within the 2.5V range of input voltage: ΔQINJ =QINJ (2.5V)–QINJ (0V) and yields a value of –6.7 fC. The following equation determines the residual effective leakage current from the acquired values of peak voltage drop at a repetition rate of 160 Hz: ILEAK =CH ×VDROPPEAK ×fREP , where ILEAK is the leakage current. A leakage current at the input voltage of 0V is approximately 17 pA, and a leakage current at the input voltage of 2.5V is approximately –17 pA.

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